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L6246
12V VOICE COIL MOTOR DRIVER
12V (10%) OPERATION 3A MAXIMUM CURRENT CAPABILITY 0.3 MAXIMUM ON RESISTANCE OF EACH POWER DMOS AT A JUNCTION TEMPERATAURE OF 25C CLASS AB POWER AMPLIFIERS LOGIC AND POWER SUPPLY MONITOR POWER ON RESET PARKING FUNCTION WITH SELECTABLE RETRACT VOLTAGE AND DYNAMIC BRAKE BEFORE PARKING ENABLE FUNCTION GATE DRIVER FOR EXTERNAL BLOCKING N-MOSFET OVERTEMPERATURE PROTECTION OVERTEMPERATURE WARNING OUTPUT PQFP44 PACKAGE MULTIPOWER BCD TECHNOLOGY
PQFP44 (10x10)
DESCRIPTION The voice coil driver L6246 is a linear power amplifier designed to drive single phase bipolar DC motors for hard disk drive applications. The device contains a selectable transconductance loop, which allows high precision for head positioning. The power stage is composed of 2 power amplifiers, in AB class, with 4 DMOSs, with Rdson of 0.5 (Sink+Source) maximum, in a H-bridge con-
figuration. Drive voltage for the upper DMOS FETs is provided by a charge pump circuit to ensure low Rdson. Automatic brake and parking of the head actuator is performed by logic or when a failure condition is detected by power supply monitors. An external resistor programs the parking voltage that enables the head retract. In addition, a 5V stable output is provided for the external usage, and a gate driver circuit enables an external power supply isolation N-MOSFET. This device is built in BCD II technology allowing dense digital circuitry to be combined with high power bipolar power devices and is assembled in PQFP44.
February 1998
1/12
L6246
PIN CONNECTION (Top view)
GATE DRIVE CPGND
OUT+
OUT-
GND
44 43 42 41 40 39 38 37 36 35 34 N.C. FILTER_CAP BRAKE DELAY -THERMAL SD SENSE-IN+ SENSE-INGND ERR-OUT ERRSENSE-OUT N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 VINVIN+ VCC/2 -AE_W_GATE -POR VDD VCC MOTOR START VIN_OUT +5V REF T_CAP 33 32 31 30 29 28 27 26 25 24 23 N.C. ENABLE -SPINDLE START VCM PARK -W_GATE RPARK VBEMF +12SETPT +5SETPT +5V REF_GND N.C.
GND
VCP
VCC
VCC
C2
C1
D95IN241B
BLOCK DIAGRAM
CP_GND GATE DRIVE -SPINDLE START MOTOR -AE START -W_GATE W_GATE VCM PARK INPUT AMPLIFIER C1 C2 VCP CHARGE PUMP GATE DRIVER
VINVIN+ VIN_OUT -POR
VCC
+5 4A 10K 10K REF1 10K + BRAKE CIRCUIT POWER AMPLIFIERS VCC BRAKE DELAY 30K 25K THERMAL -THERMAL SD
+12 FILTER CAP
+ -
VDD
20K
+5 FILTER CAP
+ +
T_CAP
REF1 PARKING VPARK VCC/2 + -
OUT+
RPARK ERR_OUT VCC/2 ERR+ ERROR AMPL.
GND VCC SENSE AMPLIFIER
+ REF1 +5V REF +5V REF_GND REF. VOLT. GENERATOR V CC/2 SENSE _IN+ SENSE _IN-
+ -
OUT-
GND
SENSE_ OUT
VBEMF
D95IN242B
2/12
L6246
ABSOLUTE MAXIMUM RATINGS
Symbol Vpow. max. Vdigital max. Vin max. Vin min. Ipeak Idc Ptot Top Maximum supply voltage Maximum supply voltage Maximum input voltage Minimum input voltage Peak sink/source output current DC sink/source output current Maximum total power dissipation Operative temperature range Parameter Value 15 7 Vdigital 0.3 GND - 0.3 3 1.7 1.7 0 to 80 Unit V V V V A A W C
THERMAL DATA
Symbol Rth j-case Rth j-amb Rth j-amb Parameter Thermal resistance junction to case Thermal resistance junction to ambient mounted on standard PCB (*) Thermal resistance junction to ambient mounted on PCB (**) Value 20 66 35 Unit C/W C/W C/W
(*) Standard board construction: single layer (1S 0P); size 100mm long by 100mm wide. (**) The board construction includes: a 6 layer board (2S 4P, with power planes 80%); size 136mm long by 99mm wide; package location near middle point of lenght and one third of width.
PIN FUNCTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name N.C. Filter_cap Brake Delay -Thermal SD Sense_in+ Sense_inGnd Err_out ErrSense_out N.C. Vin_out VinVin+ +Vcc/2 +Motor start -AE_W_Gate +Vdd +Vcc -POR +5V Ref T_cap N.C. +5V Ref Gnd +5Setpt Not Connected. Filter capacitor for 10V internal regulator. The capacitor is optional. Voice Coil Motor brake delay capacitor. Pre Thermal Shut Down indication Output. Non inverting Input of Sense Amplifier. Inverting Input of Sense Amplifier. Ground. Error Amplifier Output. Inverting Input of Error Amplifier. Output of Sense Amplifier. Not Connected. Output of Input Amplifier. Inverting Input of Input Amplifier. Non inverting Input of Input Amplifier. Half Supply Voltage reference. Motor start Output to Spindle Controller. Write Gate Output to AE. +5V Supply. +12V Supply. Power On Reset. Low will signal the failure of the logic supply or 12V supply +5V Reference Output from the Voltage Reference Regulator. Power On Reset Timing Capacitor. The capacitor sets the POR delay. Not Connected. Ground for Voltage Reference Generator. +5V Monitor Set Point and filtering Description
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L6246
PIN FUNCTIONS (continued)
Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name +12Setpt Vbemf Rpark -W_Gate +VCM park -Spindle_start +Enable N.C. Cpgnd Gnd Out+ Vcc C1 C2 Vcp Vcc OutGnd Gate Drive +12V Monitor Set Point and filtering Input BEMF from spindle motor for parking circuit. Resistor for setting the park voltage. Write Gate Input. External input for parking. High will activate the park procedure. Spindle Start input. Input. logic low will disable only the IC. Not Connected. Charge Pump Ground. Ground. Power Amplifier Output. +12V Power Supply. Charge Pump Oscillator Output. Input for external Charge Pump Capacitor. Output for Charge Pump Storage Capacitor. +12V Power Supply. Power Amplifier Output. Ground. Gate Drive for External Isolation N-MOSFETS. Description
ELECTRICAL CHARACTERISTICS (Tj = 25C, Vdd = 5V, Vcc = 12V; unless otherwise specified.)
Symbol Vcc Vdd Idd Idd Icc Icc Th_SD Th_SD_H Th_Warn Parameter Analog/Power supply voltage range Digital supply voltage range Digital supply quiescent current Digital supply quiescent current Power supply quiescent current Power supply quiescent current Shut down Temperature Shut down hysteresys Pre Shut down alarm Pre Shut down alarm hysteresys EXTERNAL N-MOSFET GATE DRIVER Vll Vhl Isink Isource Vdd_und_th Vcc_und_th POR_to POR _delay Vdd_POR_T_R Low level voltage High level voltage Current sinking capability Current source capability Digital undervoltage threshold Power undervoltage threshold POR timeout Time delay for POR Active Power supply POR thereshold Resistance 10 Cpor = 1F 3.8 8.5 375 Vcc+4 4 0.5 4.1 9.25 500 4.45 10.0 625 1 500 mV V mA mA V V ms s K 115 Output ENABLED Output DISABLED Output ENABLED Output DISABLED 135 Test Condition Min. 10.8 4.5 Typ. 12 5 5 5 20 10 160 25 140 15 Max. 13.2 5.5 Unit V V mA mA mA mA C C C C
THERMAL SHUT DOWN DATA
POWER ON RESET AND GATE SPECIFICATION
4/12
L6246
ELECTRICAL CHARACTERISTICS (continued)
Symbol VCC_POR_T_R I_POR_O Voh Vol Vih Vil Vref Drift loref Vi Vcm Vds Vos Ib Gv SR GBW PSRR Vo Vi Vos Ib Gv SR GBW PSRR Vo Parameter Logic supply POR thereshold Resistance POR output current drive CMOS high level output voltage CMOS low level output voltage TTL high level input voltage TTL low level input voltage Voltage reference at Power On Drift from Power On Current output Input voltage range Input common mode voltage range Input differential voltage swing Input offset voltage Input Bias current Open Loop voltage Gain Output slew rate Gain bandwidth product Power supply rejection ratio Output voltage swing Input voltage range Input offset voltage Input Bias current Open Loop voltage Gain Output slew rate Gain bandwidth product Power supply rejection ratio Output voltage swing 4.75 -2 10 Vref (-) 0 -5 -5 -500 80 0.6 1 80 9 VCC/2 -0.5 -5 -500 80 0.6 1 80 VCC/2 -2Vbe Gnd -6 -1.5 50 9.9 3 1 Gv = 10(V/V) -0.35 56 +0.55 10 10.1 VCC/2 +2Vbe Vcc +6 +1.5 VCC/2 +0.5 +5 +500 Vref (+) 5.00 +5 +5 +500 5.00 Iout = 1.0mA Iout = 1.0mA 2 0.80 5.25 +2 Test Condition Min. 10 4 4.10 0.40 Typ. Max. Unit K mA V V V V V % mA V V V mV nA dB V/s MHz dB V V mV nA dB V/s MHz dB V
LOGIC INTERFACE VOLTAGE LEVEL (All digital inputs are CMOS compatible)
5V REFERENCE GENERATOR
INPUT AMPLIFIER
ERROR AMPLIFIER
SENSE AMPLIFIER Vi Vos Ii PSRR Gv Rin GBW Vli CMRR Input voltage range Input offset voltage Input sink and source current Power supply rejection ratio Vloltage gain Differential input resistance Gain bandwidth product Linear differential input voltage range Common mode rejection ratio V mV mA dB V/V K MHz V dB
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L6246
ELECTRICAL CHARACTERISTICS (continued)
Symbol POWER AMPLIFIER Rdson Gdv Iol SR Tsr GBW RETRACT Vr Vr Cs Vs Cp Max. retract voltage Max. retract voltage Storage capacitor Storage voltage Pump capacitor Vcc +4 0.2 Vcc shorted to GND Vcc Normal 300 1 1 mV V F V F DMOS on resistance Differential voltage gain Output current leakage Output slew rate Saturation recovery time Gain bandwidth product 100 0.4 5 at 25C 32 500 0.3 V/V A V/s s KHz Parameter Test Condition Min. Typ. Max. Unit
CHARGE PUMP
RETRACT TRUTH TABLE
Input -Retract Brake and Retract Run Disable 0 1 1 Input +Enable X 1 0 Output Bridge Enable 0 1 0 Output +Retract 1 0 0
BLOCK DESCRIPTION POWER AMPLIFIERS The two power amplifiers are connected in bridge configuration working in AB class. SENSE AMPLIFIER This stage senses the voltage drop across the Rsense. The input stage is supplied by the charge pump voltage to have an high dynamic, while the other sections of the amplifier are supplied by the voltage of 10.5V internally regulated to have an high power supply rejection (this voltage, supplies also the error amplifier, the input amplifier and the operational amplifier which generates the Vcc/2 voltage). The open loop gain is around 80dB and the bandwith is more than 1MHz. The voltage gain is fixed internally at 10 V/V. ERROR AMPLIFIER This is the stage which compares the input voltage and the sense voltage, generating the control voltage for the power section.
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The open loop gain and bandwith of this amplifier are similar to the sense amplifier. The negative input and the output of the error amplifier are accessible externally in order to have the current loop compensation user configurable. The dynamic of the output is limited at +/- 2Vbe to have a faster response of the output voltage. INPUT AMPLIFIER The inputs and the output pins are externally accessible to have the possibility to configure the transconductance gain of the current control loop selecting the voltage gain of this amplifier. The open loop gain and bandwith of this amplifier are similar to the sense amplifier. REFERENCE VOLTAGE GENERATOR This block generates the two reference voltage Vcc/2 and +5VREF. The Vcc/2 voltage is used as reference by the current control loop. The +5VREF is a very stable voltage generator that can be used as reference voltage of an external DAC.
L6246
POWER SUPPLY MONITOR This circuit monitors the logic supply (5V) and the power supply (12V) and activates the power on reset output (POR) and the VCM PARK circuit. After both logic and power supply reach their nominal value a timing capacitor (T_CAP) has to be charge before the POR output change from low to high level. POR delay= CV I Vr is the retract voltage for parking the heads Vbandgap is the internal bandgap reference voltage of 1.4V Rpark is value of the resistor connected at RPARK pin The parking circuit takes the power supply from the spindle driver through the VBEMF pin, so that in case of power fail the retract of the heads is possible using the rectified BEMF voltage coming from the spindle motor. CHARGE PUMP The charge pump circuit is used as a means of almost doubling the power supply voltage (12V) in order to drive the upper DMOS of the power bridge. The energy stored in the in the capacitor connected at VCP pin is also used to drive the gate of the external N-MOSFET. GATE DRIVER This circuit provide the voltage driving the gate of the external isolation N-MOSFET, and it is controlled by the POR signal. THERMAL The thermal protection circuit has two threshold, the first if the pre shut down alarm that activates the THERMAL SD signal and the second is the shut down temperature that tristates the output stage when the junction temperature increases over this level. APPLICATION INFORMATION Example of calculation of the error amplifier compansation for the stability of the current control loop. As can be seen from the draw of the current control loop circuit of the next page, the voltage across the load is: #1 VL = ACPW ACERR (ACINP VIN - ACENSE Vsense) Vsense = Rs IL VL = ( ZL + Rs) IL where AC... is the closed loop gain of Power, Error, Sense and Input Amplifier. Changing in the #1 the transfer function between the load current and the VIN is: #2
where: C is the capacitor value connected at pin T_CAP V is delta voltage that capacitor have to be charged (2.3V) I is the costant current charging the capacitor (4A typ.) At the two input pins, +12 FILTER CAP and + 5 FILTER CAP, can be connected two capacitors for filtering the noise on the power supply, avoiding in this case undesired commutations of the POR signal because of some fast negative spikes on the line. BRAKE AND PARKING CIRCUITS The voice coil driver is switched into the parking condition through the VCM PARK input or when the POR signal is low. In such condition immediately the output stage turns on the two lower DMOS of the power bridge to activate the BRAKE of the voice coil motor. After a delay generated by the capacitor at the BRAKE DELAY pin, only one of the two lower DMOS stays on while the opposite half bridge is tristated. BRAKE delay = CV I
where: C is the capacitor value connected at pin BRAKE DELAY V is delta voltage that capacitor have to be charged (3V) I is the costant current charging the capacitor (5A typ.) The parking voltage is then supplied by the PARKING circuit connected to the output that has been tristated. The value of such a voltage is set by connecting an external resistor between the RPARK pin and ground. Vr = where:
Vbandgap 104
Rpark
ACPW ACERR ACINP IL = VIN ZL + RS + ACPW ACERR ACSENSE RS
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L6246
Typical Application Circuit
VOICE COIL MOTOR LL RL Rs 0.2 OUT_ SENSE_OUT ERR_OUT 1K 1M 1K 100nF ERRVIN_OUT 10K 10K VCTL 10K VREF 10K VCC/2 VCC/2 CPGND GND 15 34 7,35,43 17 16 4 20 FILTER_CAP (*)
FILTER CAPACITORS TO BE SET IN APPLICATION
VDD 100nF 10nF
SENSE_IN42 6 5
SENSE_IN+ 36
OUT+ 18
VDD 38
C1 39
C2 19 41 37
V CC V CC V CC 22F GATE DRV 100nF G
VCC
10 8
9
44
S D
P322 FROM SPINDLE DRIVER
1K
27 12 40 28 13 VIN+ 14
V BEMF V CP R PARK 5VREF 5VREF GND (*) 12SEPT 5SSEPT 12SEPT 5SSEPT (*) 1F 51K
100nF
VIN-
L6246
PQFP44
21 24 26
5VREF GND
25
1F
AE W GATE MOTOR START THERMAL SHTD POR 10.5V INT.REG.
22
1F 3 32 30
ENABLE VCM PARK SPINDLE START W GATE
D95IN268
2
31 29
Current Control Loop Circuit
VCC/2 + 10VSENSE 20K 2K V SENSE 2K 20K VCC/2 RA RB VIN RB RA VCC/2 + INPUT AMPL. + SENSE AMPL. R1 V CC/2
VCC/2 + (RA/RB) (ZC/RC) VIN-10 (ZC/R1) VSENSE
+ -
ERROR AMPL.
TO SENSE
- AMPLIFIER +
17.5K ZC 1.1K VCC/2 + POWER AMPL. RS LL LOAD VL 16.5K
R2 C R3
RL
-
RC (=R1)
-
+
+ POWER AMPL. 1.1K
VCC/2 VL=32 ( (ZC/RC) VIN - 10 (ZC/R1) VSENSE ) VCC/2 - (RA-RB) VIN
D95IN269B
= ACPW * ACERR ( ACIMP * VIN - ACSENSE * VSENSE )
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L6246
If Now We Define: #3 Aloop = ACPW ACERR ACSENSE we obtain: #4 RS RS + ZL and its pole is at frequency 1 2 L (RS + RL)
so around 1KHz if L = 1.2mH. So considering: Ax | dB = Aloop |
dB
ACERR | dB ACPW | RS dB RS + RL
ACINP 1 Aloop ACSENSE RS IL = VIN 1 + Aloop
dB+
ACSENSE | dB +
Atlowfrequencyis: Aloop = 32
we have these Bode diagrams:
R2
R1
10
RS
(RS + ZL)
ACPW
if R2 = 1M, R1 = 1K, RS = 0.2, RL = 7 then Aloop = 8889 = 80dB. Being Aloop very high we can simplify the #4 in this way: IL ACINP 1 1 1 = = = VIN ACSENSE RS 10 0.2 2 For the stability we have to study the stability of Aloop, that as we can see from the #3 is a multiplication, so in dB is a sum:
30dB
130KHz
ACSENSE 210KHz
20dB
-31dB
Aloop |
dB
dB
= ACPW |
dB+ACERR
|
dB+ACSENSE
|
LOAD AX
+
RS dB RS + ZL
19dB
So we can take in consideration the BODE diagrams of the each operational amplifier, with particular attention to the Error amplifier. 1)The Power amplifier is actually composed by two operational amplifiers in the way to have a gain of +16 and -16 (in voltage) respectevely, for a total of 32 = 30dB. The point at -3dB is around 130KHz. 2)The Sense amplifier has a gain of 20dB with the point at -3dB around 210KHz. 3)The load introduce an attenuationof: RS = -31dB with RS = 0.2 and RL = 7 RS + RL
1K
10K
100K
D95IN270A
20log
As can be easily see the bandwith is narrow and the gain is low. It is possible to increase both choosing an appropriate compensation of the Error amplifier. The total bandwith should be, of course, at least a decade lower of the 130KHz to avoid instability problem. The bandwith guaranteed by the Error amplifier has a Gmax of 80dB and a gain of 0dB at 1MHz approximately, the real is some dB more with a larger bandwith.
9/12
L6246
As can be seen the choice of the pole influence overall in fixing the gain at high frequency. The gain at high frequency must be choosen in order to not create instability problem, because more higher is this gain and lower is the second pole that we have at high frequency. If this pole is taken close to the other that we have already seen at 130KHz and 210KHz, instability problems can arise. Adding together AX | dB and ACERR | dB we obtaine the Aloop:
ACERR (dB)
ERROR AMPL. GAIN (dB) OPEN LOOP GAIN
120 100 80 60 40 20
COMPENSATION AT 3Hz
D95IN271
1
10
100
1K
10K
100K
1M
10M
60 40 20
COMPENSATION AT 100Hz
Using the compensation network of the draw of pag.8, we have a error amplifier transfer function of: 1 + scR3 VO ZC R2 =- =- VI R1 R1 1 + sc (R3 + R2) so: R2 Gmax (DC) = = 1000 = 60dB R1 with R1 = 1M and R2 = 1K 1 2 R3C 1 pole = 2 (R3 + R2) C zero =
Note: Fpole is lower than Fzero
AX(dB)
19
ALOOP (dB) 79 60 40 20 IS STABLE IS NOT STABLE
D95IN273
10
100
1K
10K
100K
1M
10M
So the choice of the compensation network must be done in order to fix at the beginning the Gmax of the error amplifier depending on the ratio R2 . R1
The best choice is to cancel the pole of the load (at around 1KHz) with the zero of the compensation.
To calculate the R3 and C values satisfying the following system: 1 2L 1 = 2 R3C RL + Rsense Error amplifier zero equal to load pole
ACERR (dB)
120 100
X
DIFFERENTS POLES EXAMPLES
80
X
1 Admissible Bandwith = = Gloop 2 (R3 + R2)C 130KHz 10 = = 1.5Hz 8912
60 40 20 CLOSED LOOP ACERR 1 10 100 1K 10K 100K
X
D95IN272
1M
10M
This example is for crossing the 0dB one decade before the first pole of the Power Amplifier (130KHz), starting with a Gloop max of 79dB.
10/12
L6246
PQFP44 (10x10) PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B c D D1 D3 e E E1 E3 L L1 K 0.65 12.95 9.90 0.25 1.95 0.30 0.13 12.95 9.90 13.20 10.00 8.00 0.80 13.20 10.00 8.00 0.80 1.60 0(min.), 7(max.) 0.95 0.026 13.45 10.10 0.510 0.390 2.00 2.10 0.45 0.23 13.45 10.10 mm TYP. MAX. 2.45 0.010 0.077 0.012 0.005 0.51 0.390 0.52 0.394 0.315 0.031 0.520 0.394 0.315 0.031 0.063 0.037 0.530 0.398 0.079 0.083 0.018 0.009 0.53 0.398 MIN. inch TYP. MAX. 0.096
D D1 D3 A1
33 34 23 22
0.10mm .004 Seating Plane
A A2
E3
E1
B
44 1 11
12
E
B C L K
e L1
PQFP44
11/12
L6246
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1998 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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